98 search results - page 13 / 20 » Memory Access Scheduling Schemes for Systems with Multi-Core... |
DAC
2002
ACM
14 years 8 months ago
2002
ACM
Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operatin...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
CCGRID
2009
IEEE
14 years 2 months ago
2009
IEEE
In a cluster of multiple processors or cpu-cores, many processes may run on each compute node. Each process tends to issue contiguous I/O requests for snapshot, checkpointing or s...
CLUSTER
2008
IEEE
14 years 1 months ago
2008
IEEE
—User-level communication allows an application process to access the network interface directly. Bypassing the kernel requires that a user process accesses the network interface...