117 search results - page 11 / 24 » Memory Access Schemes for Configurable Processors |
DATE
2010
IEEE
14 years 24 days ago
2010
IEEE
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
CODES
2008
IEEE
14 years 2 months ago
2008
IEEE
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
ISCA
1999
IEEE
13 years 12 months ago
1999
IEEE
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
HPCA
2007
IEEE
14 years 2 months ago
2007
IEEE
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...
GLOBECOM
2007
IEEE
14 years 2 months ago
2007
IEEE
— In this paper, we propose a novel supernode caching scheme to reduce IP lookup latencies and energy consumption in network processors. In stead of using an expensive TCAM based...