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HIPC
2007
Springer
14 years 1 months ago
Self-optimization of Performance-per-Watt for Interleaved Memory Systems
- With the increased complexity of platforms coupled with data centers’ servers sprawl, power consumption is reaching unsustainable limits. Memory is an important target for plat...
Bithika Khargharia, Salim Hariri, Mazin S. Yousif
HPCA
2005
IEEE
14 years 8 months ago
Tapping ZettaRAMTM for Low-Power Memory Systems
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Roten...
MICRO
2006
IEEE
155views Hardware» more  MICRO 2006»
14 years 1 months ago
In-Network Cache Coherence
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
Noel Eisley, Li-Shiuan Peh, Li Shang
OSDI
1994
ACM
13 years 9 months ago
Opportunistic Log: Efficient Installation Reads in a Reliable Storage Server
In a distributed storage system, client caches managed on the basis of small granularity objects can provide better memory utilization then page-based caches. However, object serv...
James O'Toole, Liuba Shrira
EP
1998
Springer
14 years 20 hour ago
Memory Scalability in Constraint-Based Multimedia Style Sheet Systems
Abstract. Multimedia style sheet systems uniformly use a constraintbased model of layout. Constraints provide a uniform mechanism for all aspects of style management and layout and...
Terry Cumaranatunge, Ethan V. Munson