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ASPLOS
1992
ACM
13 years 12 months ago
Application-Controlled Physical Memory using External Page-Cache Management
Next generation computer systems will have gigabytes of physical memory and processors in the 200 MIPS range or higher. While this trend suggests that memory management for most p...
Kieran Harty, David R. Cheriton
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
14 years 1 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
TVLSI
2008
169views more  TVLSI 2008»
13 years 7 months ago
Energy-Aware Flash Memory Management in Virtual Memory System
The traditional virtual memory system is designed for decades assuming a magnetic disk as the secondary storage. Recently, flash memory becomes a popular storage alternative for ma...
Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng
IPPS
2000
IEEE
14 years 4 days ago
Fault-Tolerant Distributed-Shared-Memory on a Broadcast-Based Interconnection Network
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
Diana Hecht, Constantine Katsinis
ASPLOS
2006
ACM
14 years 1 months ago
Software-based instruction caching for embedded processors
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
Jason E. Miller, Anant Agarwal