16 search results - page 3 / 4 » Memory Modeling in ESL-RTL Equivalence Checking |
ENTCS
2007
13 years 7 months ago
2007
Much of the literature on symmetry reductions for model checking assumes a simple model of computation where the local state of each component in a concurrent system can be repres...
DSD
2004
IEEE
13 years 11 months ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
DAC
1996
ACM
13 years 11 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
PPOPP
2009
ACM
14 years 8 months ago
2009
ACM
This paper considers the problem of formal verification of MPI programs operating under a fixed test harness for safety properties without building verification models. In our app...