Instruction fetch behavior has been shown to be very regular and predictable, even for diverse application areas. In this work, we propose the Lookahead Instruction Fetch Engine (...
Stephen Roderick Hines, Yuval Peress, Peter Gavin,...
— Many important applications are organized around long-lived, irregular sparse graphs (e.g., data and knowledge bases, CAD optimization, numerical problems, simulations). The gr...
Michael DeLorimier, Nachiket Kapre, Nikil Mehta, D...
As the disparity between processor and main memory performance grows, the number of execution cycles spent waiting for memory accesses to complete also increases. As a result, lat...
Teresa L. Johnson, Matthew C. Merten, Wen-mei W. H...
Non-volatile RAM (NVRAM) such as PRAM (Phase-change RAM), FeRAM (Ferroelectric RAM), and MRAM (Magnetoresistive RAM) has characteristics of both non-volatile storage and random ac...
In Hwan Doh, Jongmoo Choi, Donghee Lee, Sam H. Noh
In this paper, we present a shared instruction and data memory controller for the On-Chip Memory (OCM) bus of the PowerPC embedded in the Virtex-4 chip. The traditional design of ...