276 search results - page 47 / 56 » Memory Organization for Improved Data Cache Performance in E... |
ICALP
2010
Springer
13 years 10 months ago
2010
Springer
We present a new deterministic sorting algorithm that interleaves the partitioning of a sample sort with merging. Sequentially, it sorts n elements in O(n log n) time cache-oblivi...
IWMM
2009
Springer
14 years 3 months ago
2009
Springer
Tracing algorithms visit reachable nodes in a graph and are central to activities such as garbage collection, marshalling etc. Traditional sequential algorithms use a worklist, re...
ASPLOS
2010
ACM
13 years 11 months ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
ACMMSP
2004
ACM
14 years 1 months ago
2004
ACM
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
HPCA
2004
IEEE
14 years 8 months ago
2004
IEEE
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...