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TII
2010
124views Education» more  TII 2010»
13 years 2 months ago
Address-Independent Estimation of the Worst-case Memory Performance
Abstract--Real-time systems are subject to temporal constraints and require a schedulability analysis to ensure that task execution finishes within lower and upper specified bounds...
Basilio B. Fraguela, Diego Andrade, Ramon Doallo
MICRO
2006
IEEE
79views Hardware» more  MICRO 2006»
14 years 1 months ago
Fair Queuing Memory Systems
We propose and evaluate a multi-thread memory scheduler that targets high performance CMPs. The proposed memory scheduler is based on concepts originally developed for network fai...
Kyle J. Nesbit, Nidhi Aggarwal, James Laudon, Jame...
MICRO
1998
IEEE
89views Hardware» more  MICRO 1998»
13 years 12 months ago
Load Latency Tolerance in Dynamically Scheduled Processors
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
Srikanth T. Srinivasan, Alvin R. Lebeck
JTRES
2010
ACM
13 years 8 months ago
Exhaustive testing of safety critical Java
With traditional testing, the test case has no control over non-deterministic scheduling decisions, and thus errors dependent on scheduling are only found by pure chance. Java Pat...
Tomás Kalibera, Pavel Parizek, Michal Maloh...
MICRO
2002
IEEE
143views Hardware» more  MICRO 2002»
14 years 18 days ago
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor
Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functio...
Enric Gibert, F. Jesús Sánchez, Anto...