3202 search results - page 438 / 641 » Memory access scheduling |
145
Voted
EMSOFT
2005
Springer
15 years 8 months ago
2005
Springer
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
100
Voted
VLDB
2004
ACM
15 years 8 months ago
2004
ACM
Online transaction processing (OLTP) is a multibillion dollar industry with high-end database servers employing state-of-the-art processors to maximize performance. Unfortunately,...
134
Voted
USENIX
1996
15 years 4 months ago
1996
This paper describes a new method for providingtransparent fault tolerance for parallel applications on a network of workstations. We have designed our method in the context of sh...
126
Voted
IJHPCA
2010
15 years 1 months ago
2010
Sparse matrix operations achieve only small fractions of peak CPU speeds because of the use of specialized, indexbased matrix representations, which degrade cache utilization by i...
110
Voted
ICCAD
2002
IEEE
15 years 11 months ago
2002
IEEE
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...