3202 search results - page 6 / 641 » Memory access scheduling |
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
ICDCS
1996
IEEE
13 years 12 months ago
1996
IEEE
Efficiently scheduling parallel tasks on to the processors of a shared-memory multiprocessor is critical to achieving high performance. Given perfect information at compile-time, ...
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
With wide adoption of chip multiprocessors (CMPs) in modern computers, there is an increasing demand for large capacity main memory systems. The emerging PCM (Phase Change Memory) ...
RTSS
2007
IEEE
14 years 1 months ago
2007
IEEE
In multiprocessor systems, the traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers a...
ISCA
2008
IEEE
14 years 2 months ago
2008
IEEE
Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance chip multiprocessors (CMPs). Conventional memory controllers deli...