110 search results - page 6 / 22 » Memory hierarchy exploration for low power architectures in ... |
LCTRTS
2007
Springer
14 years 25 days ago
2007
Springer
As memory speeds and bus capacitances continue to rise, external memory bus power will make up an increasing portion of the total system power budget for system-on-a-chip embedded...
ISLPED
2005
ACM
14 years 8 days ago
2005
ACM
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
AES
2005
Springer
13 years 6 months ago
2005
Springer
Media-processing applications, such as signal processing, 2D and 3D graphics rendering, and image compression, are the dominant workloads in many embedded systems today. The real-...
CASES
2004
ACM
14 years 4 days ago
2004
ACM
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of...
VLSID
2001
IEEE
14 years 7 months ago
2001
IEEE
Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizationsfor programmable systems assumed a fixed cache hierarchy. Withthe wideningproce...