122 search results - page 17 / 25 » Memory models for open-nested transactions |
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
ISCA
1993
IEEE
13 years 11 months ago
1993
IEEE
Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective u...
POPL
2009
ACM
14 years 8 months ago
2009
ACM
Speed improvements in today's processors have largely been delivered in the form of multiple cores, increasing the importance of ions that ease parallel programming. Software...
HPCA
2006
IEEE
14 years 8 months ago
2006
IEEE
Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed a...
PODC
2005
ACM
14 years 1 months ago
2005
ACM
In recent software transactional memory proposals, a contention manager module is responsible for ensuring that the system as a whole makes progress. A number of contention manage...