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» Memory testing with a RISC microcontroller
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DATE
2010
IEEE
120views Hardware» more  DATE 2010»
14 years 4 months ago
Memory testing with a RISC microcontroller
—Many systems are based on embedded microcontrollers. Applications demand for production and Power-On testing, including memory testing. Because low-end microcontrollers may not ...
A. J. van de Goor, Georgi Gaydadjiev, Said Hamdiou...
ET
2008
92views more  ET 2008»
13 years 10 months ago
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware harde...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
FDTC
2010
Springer
124views Cryptology» more  FDTC 2010»
13 years 9 months ago
Optical Fault Masking Attacks
This paper introduces some new types of optical fault attacks called fault masking attacks. These attacks are aimed at disrupting of the normal memory operation through preventing ...
Sergei Skorobogatov
DATE
2008
IEEE
138views Hardware» more  DATE 2008»
14 years 5 months ago
Functional Self-Testing for Bus-Based Symmetric Multiprocessors
Functional, instruction-based self-testing of microprocessors has recently emerged as an effective alternative or supplement to other testing approaches, and is progressively adop...
Andreas Apostolakis, Dimitris Gizopoulos, Mihalis ...
IPSN
2007
Springer
14 years 5 months ago
Harbor: software-based memory protection for sensor nodes
Many sensor nodes contain resource constrained microcontrollers where user level applications, operating system components, and device drivers share a single address space with no...
Ram Kumar, Eddie Kohler, Mani B. Srivastava