Sciweavers

69 search results - page 13 / 14
» Memory-aware Scheduling for Energy Efficiency on Multicore P...
Sort
View
PACS
2000
Springer
110views Hardware» more  PACS 2000»
13 years 11 months ago
Compiler-Directed Dynamic Frequency and Voltage Scheduling
Dynamic voltage and frequency scaling has been identified as one of the most effective ways to reduce power dissipation. This paper discusses a compilation strategy that identifies...
Chung-Hsing Hsu, Ulrich Kremer, Michael S. Hsiao
ISLPED
2010
ACM
158views Hardware» more  ISLPED 2010»
13 years 7 months ago
Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach
The ongoing scaling of semiconductor technology is causing severe increase of on-chip power density and temperature in microprocessors. This has raised urgent requirement for both...
Weixun Wang, Xiaoke Qin, Prabhat Mishra
ISLPED
2010
ACM
169views Hardware» more  ISLPED 2010»
13 years 7 months ago
TurboTag: lookup filtering to reduce coherence directory power
On-chip coherence directories of today's multi-core systems are not energy efficient. Coherence directories dissipate a significant fraction of their power on unnecessary loo...
Pejman Lotfi-Kamran, Michael Ferdman, Daniel Crisa...
DAC
2008
ACM
13 years 9 months ago
Application mapping for chip multiprocessors
The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fas...
Guangyu Chen, Feihui Li, Seung Woo Son, Mahmut T. ...
EMSOFT
2010
Springer
13 years 5 months ago
Energy-aware packet and task co-scheduling for embedded systems
A crucial objective in battery operated embedded systems is to work under the minimal power consumption that provides a desired level of performance. Dynamic Voltage Scaling (DVS)...
Luca Santinelli, Mauro Marinoni, Francesco Prosper...