60 search results - page 4 / 12 » Memory-constrained Block Processing for DSP Software Optimiz... |
HIPEAC
2007
Springer
14 years 1 months ago
2007
Springer
The XScale processor family provides user-controllable independent configuration of CPU, bus, and memory frequencies. This feature introduces another handle for the code optimizat...
CODES
2003
IEEE
14 years 23 days ago
2003
IEEE
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
DAC
1995
ACM
13 years 11 months ago
1995
ACM
High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain. Both application-speci c integrated circuits (ASICs) and application-...
ISCAS
2002
IEEE
14 years 12 days ago
2002
IEEE
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
SCOPES
2005
Springer
14 years 28 days ago
2005
Springer
Specification, validation, and synthesis are important aspects of embedded systems design. The use of dataflow-based design environments for these purposes is becoming increasingl...