501 search results - page 43 / 101 » Methods for true power minimization |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a t...
MVA
2007
13 years 9 months ago
2007
In the last few years, computer vision and image processing techniques have been developed to solve many problems. One of them, graph cut method is powerful optimization technique...
ISVLSI
2002
IEEE
14 years 16 days ago
2002
IEEE
Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be re...
CVPR
2009
IEEE
15 years 2 months ago
2009
IEEE
This paper presents a solution to the problem of pose estimation
in the presence of heavy radial distortion and a potentially
large number of outliers. The main contribution is
...
SDM
2010
SIAM
13 years 6 months ago
2010
SIAM
A popular approach for dimensionality reduction and data analysis is principal component analysis (PCA). A limiting factor with PCA is that it does not inform us on which of the o...