96 search results - page 5 / 20 » Microarchitectural techniques for power gating of execution ... |
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimization...
ISCA
2003
IEEE
14 years 23 days ago
2003
IEEE
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processo...
HPCA
2012
IEEE
12 years 3 months ago
2012
IEEE
Conventional out-of-order processors that use a unified physical register file allocate and reclaim registers explicitly using a free list that operates as a circular queue. We ...
HIPEAC
2005
Springer
14 years 1 months ago
2005
Springer
We present and evaluate the TILA-rin GPU microarchitecture for embedded systems using the ATTILA GPU simulation framework. We use a trace from an execution of the Unreal Tournament...
HPCA
2003
IEEE
14 years 7 months ago
2003
IEEE
Increasing focus on power dissipation issues in current microprocessors has led to a host of proposals for clock gating and other power-saving techniques. While generally effectiv...