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ICCAD
2006
IEEE
169views Hardware» more  ICCAD 2006»
14 years 4 months ago
Microarchitecture parameter selection to optimize system performance under process variation
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
Xiaoyao Liang, David Brooks
MICRO
1993
IEEE
127views Hardware» more  MICRO 1993»
13 years 11 months ago
An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors
The conventional classification of inter-instruction dependencies (data, anti and output dependencies) provides a basic scheme for the analysis of pipeline hazards in pipelined in...
Ing-Jer Huang, Alvin M. Despain
ISPASS
2010
IEEE
14 years 2 months ago
Demystifying GPU microarchitecture through microbenchmarking
—Graphics processors (GPU) offer the promise of more than an order of magnitude speedup over conventional processors for certain non-graphics computations. Because the ften prese...
Henry Wong, Misel-Myrto Papadopoulou, Maryam Sadoo...
IEEEPACT
2007
IEEE
14 years 1 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...
SIGMETRICS
2011
ACM
196views Hardware» more  SIGMETRICS 2011»
13 years 2 months ago
Performance analysis of the OP2 framework on many-core architectures
We present a performance analysis and benchmarking study P2 “active” library, which provides an abstraction framework for the solution of parallel unstructured mesh applicatio...
M. B. Giles, Gihan R. Mudalige, Z. Sharif, Graham ...