109 search results - page 11 / 22 » Microcode Generation for Flexible Parallel Target Architectu... |
143
Voted
ICIP
2006
IEEE
16 years 4 months ago
2006
IEEE
This paper proposes a hardware architecture of a video noise estimation algorithm capable of real-time processing. The objectives consist of adapting a computationally demanding n...
108
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CLUSTER
2006
IEEE
15 years 8 months ago
2006
IEEE
The increase in the use of parallel distributed architectures in order to solve large-scale scientific problems has generated the need for performance prediction for both determi...
114
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DATE
2002
IEEE
15 years 7 months ago
2002
IEEE
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
168
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FCCM
2011
IEEE
14 years 6 months ago
2011
IEEE
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
130
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CODES
2007
IEEE
15 years 8 months ago
2007
IEEE
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...