109 search results - page 11 / 22 » Microcode Generation for Flexible Parallel Target Architectu... |
ICIP
2006
IEEE
14 years 8 months ago
2006
IEEE
This paper proposes a hardware architecture of a video noise estimation algorithm capable of real-time processing. The objectives consist of adapting a computationally demanding n...
CLUSTER
2006
IEEE
14 years 23 days ago
2006
IEEE
The increase in the use of parallel distributed architectures in order to solve large-scale scientific problems has generated the need for performance prediction for both determi...
DATE
2002
IEEE
13 years 11 months ago
2002
IEEE
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
FCCM
2011
IEEE
12 years 10 months ago
2011
IEEE
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...