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» Migration in Single Chip Multiprocessors
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HPCA
2007
IEEE
14 years 8 months ago
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
Ricardo Fernández Pascual, José M. G...
INTEGRATION
2008
183views more  INTEGRATION 2008»
13 years 7 months ago
Network-on-Chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
David Atienza, Federico Angiolini, Srinivasan Mura...
IPPS
2010
IEEE
13 years 5 months ago
A PRAM-NUMA model of computation for addressing low-TLP workloads
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
Martti Forsell
ICS
2000
Tsinghua U.
13 years 11 months ago
Characterizing processor architectures for programmable network interfaces
The rapid advancements of networking technology have boosted potential bandwidth to the point that the cabling is no longer the bottleneck. Rather, the bottlenecks lie at the cros...
Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Bae...
CODES
2005
IEEE
14 years 1 months ago
Future processors: flexible and modular
The ability to continue increasing processor frequency and single thread performance is being severely limited by exponential increases in leakage and active power. To continue to...
Charlie Johnson, Jeff Welser