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» Migration in Single Chip Multiprocessors
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ISCA
2010
IEEE
222views Hardware» more  ISCA 2010»
13 years 9 months ago
Cohesion: a hybrid memory model for accelerators
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
John H. Kelm, Daniel R. Johnson, William Tuohy, St...
EMSOFT
2008
Springer
13 years 9 months ago
A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications
In this paper, we propose a generalized clustering approach for static data flow subgraphs mapped onto individual processors in Multi-Processor System on Chips (MPSoCs). The goal ...
Joachim Falk, Joachim Keinert, Christian Haubelt, ...
ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
13 years 7 months ago
Non-Inclusion Property in Multi-Level Caches Revisited
The center of gravity of computer architecture is moving toward memory systems. Barring breakthrough microarchitectural techniques to move processor performance to higher levels, ...
Mohamed M. Zahran, Kursad Albayraktaroglu, Manoj F...
DSD
2010
IEEE
112views Hardware» more  DSD 2010»
13 years 6 months ago
Re-NUCA: Boosting CMP Performance Through Block Replication
— Chip Multiprocessor (CMP) systems have become the reference architecture for designing micro-processors, thanks to the improvements in semiconductor nanotechnology that have co...
Pierfrancesco Foglia, Cosimo Antonio Prete, Marco ...
WWW
2005
ACM
14 years 8 months ago
A multi-threaded PIPELINED Web server architecture for SMP/SoC machines
Design of high performance Web servers has become a recent research thrust to meet the increasing demand of networkbased services. In this paper, we propose a new Web server archi...
Gyu Sang Choi, Jin-Ha Kim, Deniz Ersoz, Chita R. D...