130 search results - page 8 / 26 » Migration in Single Chip Multiprocessors |
CAL
2007
13 years 7 months ago
2007
— This paper addresses cache organization in Chip Multiprocessors (CMPs). We show that in CMP systems it is valuable to distinguish between shared data, which is accessed by mult...
CF
2009
ACM
14 years 2 months ago
2009
ACM
Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...
MICRO
2008
IEEE
14 years 2 months ago
2008
IEEE
—Efficient sharing of system resources is critical to obtaining high utilization and enforcing system-level performance objectives on chip multiprocessors (CMPs). Although sever...
VLSID
2008
IEEE
14 years 8 months ago
2008
IEEE
Worst-case execution time (WCET) analysis and, in general, the predictability of real-time applications implemented on multiprocessor systems has been addressed only in very restri...
CJ
2006
13 years 7 months ago
2006
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...