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145
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ICCAD
1997
IEEE
147views Hardware» more  ICCAD 1997»
15 years 8 months ago
Built-in test generation for synchronous sequential circuits
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
Irith Pomeranz, Sudhakar M. Reddy
ISMVL
1997
IEEE
134views Hardware» more  ISMVL 1997»
15 years 8 months ago
Functional Decomposition of MVL Functions Using Multi-Valued Decision Diagrams
In this paper, the minimization of incompletely specified multi-valued functions using functional decomposition is discussed. From the aspect of machine learning, learning sample...
Craig M. Files, Rolf Drechsler, Marek A. Perkowski
IPPS
1996
IEEE
15 years 8 months ago
A New Approach to Pipeline FFT Processor
A new VLSI architecture for real-time pipeline FFT processor is proposed. A hardware oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique ...
Shousheng He, Mats Torkelson
139
Voted
ISCAS
1994
IEEE
104views Hardware» more  ISCAS 1994»
15 years 8 months ago
A Graph-Theoretic Approach to Clock Skew Optimization
This paper addresses the problem of minimizing the clock period of a circuit by optimizingthe clock skews. We incorporate uncertainty factors and present a formulation that ensure...
Rahul B. Deokar, Sachin S. Sapatnekar
144
Voted
ACSC
2007
IEEE
15 years 7 months ago
Cross-Layer Verification of Type Flaw Attacks on Security Protocols
Security protocols are often specified at the application layer; however, application layer specifications give little detail regarding message data structures at the presentation...
Benjamin W. Long, Colin J. Fidge, David A. Carring...