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DATE
2006
IEEE
176views Hardware» more  DATE 2006»
14 years 1 months ago
Low power synthesis of dynamic logic circuits using fine-grained clock gating
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Mei...
PODC
2006
ACM
14 years 1 months ago
Quorum placement in networks: minimizing network congestion
A quorum system over a universe of logical elements is a collection of subsets (quorums) of elements, any two of which intersect. In numerous distributed algorithms, the elements ...
Daniel Golovin, Anupam Gupta, Bruce M. Maggs, Flor...
ASPDAC
2007
ACM
88views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Logic and Layout Aware Voltage Island Generation for Low Power Design
Multiple supply voltage (MSV) is one of the most effective schemes to achieve low power, but most works are based on logic level. A few recent works are based on physical level but...
Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong
SSD
2009
Springer
167views Database» more  SSD 2009»
14 years 2 months ago
Continuous Spatial Authentication
Recent advances in wireless communications and positioning devices have generated a tremendous amount of interest in the continuous monitoring of spatial queries. However, such app...
Stavros Papadopoulos, Yin Yang, Spiridon Bakiras, ...
TCAD
1998
126views more  TCAD 1998»
13 years 7 months ago
Iterative remapping for logic circuits
Abstract—This paper presents an aggressive optimization technique targeting combinational logic circuits. Starting from an initial implementation mapped on a given technology lib...
Luca Benini, Patrick Vuillod, Giovanni De Micheli