39 search results - page 2 / 8 » Minimizing the power consumption of a Chip Multiprocessor un... |
IEEEPACT
2008
IEEE
14 years 2 months ago
2008
IEEE
The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
Parameter variations are a major factor causing powerperformance asymmetry in chip multiprocessors. In this paper, we analyze the effects of with-in-die (WID) process variations o...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
— In this paper, we propose a novel, energy aware scheduling algorithm for applications running on DVS-enabled multiprocessor systems, which exploits variation in execution times...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
The application-specific multiprocessor System-on-a-Chip is a promising design alternative because of its high degree of flexibility, short development time, and potentially high ...
EMSOFT
2004
Springer
14 years 1 months ago
2004
Springer
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...