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CASES
2007
ACM
13 years 11 months ago
Fragment cache management for dynamic binary translators in embedded systems with scratchpad
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...
José Baiocchi, Bruce R. Childers, Jack W. D...
ICPP
2009
IEEE
14 years 2 months ago
Bank-aware Dynamic Cache Partitioning for Multicore Architectures
Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single c...
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. Joh...
ICCAD
2000
IEEE
135views Hardware» more  ICCAD 2000»
13 years 12 months ago
Power Optimization of Real-Time Embedded Systems on Variable Speed Processors
Power efficient design of real-time embedded systems based on programmable processors becomes more important as system functionality is increasingly realized through software. Th...
Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai
SBCCI
2005
ACM
115views VLSI» more  SBCCI 2005»
14 years 1 months ago
Design of a decompressor engine on a SPARC processor
Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumpti...
Richard E. Billo, Rodolfo Azevedo, Guido Araujo, P...
MICRO
2005
IEEE
113views Hardware» more  MICRO 2005»
14 years 1 months ago
Thermal Management of On-Chip Caches Through Power Density Minimization
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I....