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IPPS
2007
IEEE
14 years 2 months ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
ISPDC
2003
IEEE
14 years 1 months ago
OCEAN: The Open Computation Exchange and Arbitration Network, A Market Approach to Meta Computing
— Rapid advancements in processor and networking technologies have led to the evolution of cluster and grid computing frameworks. These high-performance computing environments ex...
Pradeep Padala, Cyrus Harrison, Nicholas Pelfort, ...
DCOSS
2010
Springer
14 years 1 months ago
Tables: A Spreadsheet-Inspired Programming Model for Sensor Networks
Abstract. Current programming interfaces for sensor networks often target experienced developers and lack important features. Tables is a spreadsheet inspired programming environme...
James Horey, Eric Nelson, Arthur B. Maccabe
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
14 years 2 months ago
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...
Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew...
ANCS
2007
ACM
14 years 14 days ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos