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» Modal Logics for Timed Control
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FUIN
2006
85views more  FUIN 2006»
13 years 10 months ago
Towards Integrated Verification of Timed Transition Models
Abstract. This paper describes an attempt to combine theorem proving and model-checking to formally verify real-time systems in a discrete time setting. The Timed Automata Modeling...
Mark Lawford, Vera Pantelic, Hong Zhang
TCAD
1998
125views more  TCAD 1998»
13 years 9 months ago
Test-point insertion: scan paths through functional logic
—Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are...
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-T...
DAC
2008
ACM
14 years 11 months ago
Driver waveform computation for timing analysis with multiple voltage threshold driver models
This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs...
Peter Feldmann, Soroush Abbaspour, Debjit Sinha, G...
RTCSA
2008
IEEE
14 years 4 months ago
CREAM: A Generic Build-Time Component Framework for Distributed Embedded Systems
A component framework plays an important role in CBSD as it determines how software components are developed, packaged, assembled and deployed. A desirable component framework for...
Chetan Raj, Jiyong Park, Jungkeun Park, Seongsoo H...
RTCSA
2008
IEEE
14 years 4 months ago
Power-Aware Data Buffer Cache Management in Real-Time Embedded Databases
The demand for real-time data services in embedded systems is increasing. In these new computing platforms, using traditional buffer management schemes, whose goal is to minimize ...
Woochul Kang, Sang Hyuk Son, John A. Stankovic