Sciweavers

446 search results - page 84 / 90
» Modal Logics for Timed Control
Sort
View
FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
13 years 12 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
BIRTHDAY
1991
Springer
13 years 11 months ago
The Markgraf Karl Refutation Procedure
The goal of the MKRP project is the development of a theorem prover which can be used as an inference engine in various applications, in particular it should be capable of proving ...
Hans Jürgen Ohlbach, Jörg H. Siekmann
CODES
2005
IEEE
13 years 9 months ago
FIDES: an advanced chip multiprocessor platform for secure next generation mobile terminals
We propose a secure platform on a chip multiprocessor, known as FIDES, in order to enable next generation mobile terminals to execute downloaded native applications for Linux. Its...
Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji ...
CSREAESA
2006
13 years 9 months ago
Design and Implementation of SoPC with Multi-Bus on a Chip
SoPC (System on a Programmable Chip) is one important kind of SoC solution based on PLD (Programmable Logic Device). At the same time, PBD (Platform-based Design) has become popul...
Fangjun Jian, Jizhong Han, Chengde Han, Qin Zhang,...
BROADNETS
2007
IEEE
14 years 2 months ago
Resource dimensioning in WDM networks under state-based routing schemes
— Network dimensioning for wavelength-routed WDM networks has been extensively studied to maximize connection acceptance rate while minimizing the total cost. However, Internet s...
Xiaolan J. Zhang, Sun-il Kim, Steven S. Lumetta