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DATE
2005
IEEE
112views Hardware» more  DATE 2005»
14 years 1 months ago
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in futu...
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinab...
EURODAC
1994
IEEE
141views VHDL» more  EURODAC 1994»
13 years 12 months ago
Exact path sensitization in timing analysis
of a direct implementation of this criterion. This paper presents the first critical path finding tool based on the exact criterion. It offers therefore better results in compariso...
R. Peset Llopis
TON
2008
125views more  TON 2008»
13 years 7 months ago
Two techniques for fast computation of constrained shortest paths
Abstract-- Computing constrained shortest paths is fundamental to some important network functions such as QoS routing, which is to find the cheapest path that satisfies certain co...
Shigang Chen, Meongchul Song, Sartaj Sahni
ICPR
2006
IEEE
14 years 8 months ago
Recover Writing Trajectory from Multiple Stroked Image Using Bidirectional Dynamic Search
The recovery of writing trajectory from offline handwritten image is generally regarded as a difficult problem [1]. This paper introduced a method to recover the writing trajector...
Yu Qiao, Makoto Yasuhara
ICCAD
1999
IEEE
153views Hardware» more  ICCAD 1999»
14 years 1 days ago
Cycle time and slack optimization for VLSI-chips
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
Christoph Albrecht, Bernhard Korte, Jürgen Sc...