502 search results - page 83 / 101 » Model Checking Timed Systems with Priorities |
COORDINATION
2009
Springer
14 years 8 months ago
2009
Springer
This paper presents a transactional framework for low-latency, high-performance, concurrent event processing in Java. At the heart of our framework lies Reflexes, a restricted prog...
PE
2011
Springer
13 years 2 months ago
2011
Springer
In this paper we identify a class of Quasi-Birth-and-Death (QBD) processes where the transitions to higher (resp. lower) levels are restricted to occur only from (resp. to) a subs...
TVLSI
1998
13 years 7 months ago
1998
Abstract—We introduce a technique for on-line built-in selftesting (BIST) of bus-based field programmable gate arrays (FPGA’s). This system detects deviations from the intende...
TACAS
2001
Springer
14 years 9 days ago
2001
Springer
Multi-valued logics support the explicit modeling of uncertainty and disagreement by allowing additional truth values in the logic. Such logics can be used for verification of dyn...
INFOCOM
2002
IEEE
14 years 24 days ago
2002
IEEE
This paper describes a control mechanism for a future Internet. It is an economic mechanism that enables users to choose different pairs of price/QoS priority levels for network se...