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» Model Order Reduction for Nonlinear IC Models
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DATE
1999
IEEE
92views Hardware» more  DATE 1999»
14 years 17 hour ago
Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics
Modern IC design requires accurate analysis and modeling of chip-level interconnect, the substrate and package parasitics. Traditional approaches for such analyses are computation...
Peter Feldmann, Sharad Kapur, David E. Long
JCNS
2002
99views more  JCNS 2002»
13 years 7 months ago
Coarse-Grained Reduction and Analysis of a Network Model of Cortical Response: I. Drifting Grating Stimuli
We present a reduction of a large-scale network model of visual cortex developed by McLaughlin, Shapley, Shelley, and Wielaard. The reduction is from many integrate-and-fire neuron...
Michael Shelley, David McLaughlin
INTEGRATION
2008
101views more  INTEGRATION 2008»
13 years 7 months ago
An efficient terminal and model order reduction algorithm
The paper proposes an efficient terminal and model order reduction method for compact modeling of interconnect circuits with many terminals. The new method is inspired by the rece...
Pu Liu, Sheldon X.-D. Tan, Boyuan Yan, Bruce McGau...
IJCNN
2006
IEEE
14 years 1 months ago
Nonlinear principal component analysis of noisy data
With very noisy data, having plentiful samples eliminates overfitting in nonlinear regression, but not in nonlinear principal component analysis (NLPCA). To overcome this problem...
William W. Hsieh