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» Model design using hierarchical web-based libraries
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2009
IEEE
13 years 11 months ago
Hierarchical File Systems Are Dead
For over forty years, we have assumed hierarchical file system namespaces. These namespaces were a rudimentary attempt at simple organization. As users have begun to interact with...
Margo I. Seltzer, Nicholas Murphy
PADS
1998
ACM
13 years 11 months ago
GloMoSim: A Library for Parallel Simulation of Large-Scale Wireless Networks
A number of library-based parallel and sequential network simulators have been designed. This paper describes a library, called GloMoSim (for Global Mobile system Simulator), for ...
Xiang Zeng, Rajive Bagrodia, Mario Gerla
DAC
1999
ACM
14 years 8 months ago
Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
Chung-Ping Chen, Noel Menezes
DATE
2008
IEEE
124views Hardware» more  DATE 2008»
14 years 2 months ago
Sizing Rules for Bipolar Analog Circuit Design
This paper presents sizing rules for basic building blocks in analog bipolar circuit design. Sizing rules efficiently capture design knowledge on the technology-specific level o...
Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann
DATE
2010
IEEE
138views Hardware» more  DATE 2010»
14 years 22 days ago
Checking and deriving module paths in Verilog cell library descriptions
—Module paths are often used to specify the delays of cells in a Verilog cell library description, which define the propagation delay for an event from an input to an output. Sp...
Matthias Raffelsieper, Mohammad Reza Mousavi, Chri...