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» Model-integrated parallel application synthesis
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ERSA
2007
177views Hardware» more  ERSA 2007»
13 years 9 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
ASAP
2005
IEEE
87views Hardware» more  ASAP 2005»
14 years 1 months ago
Expression Synthesis in Process Networks generated by LAURA
The COMPAAN/LAURA [18] tool chain maps nested loop applications written in Matlab onto reconfigurable platforms, such as FPGAs. COMPAAN rewrites the original Matlab application a...
Claudiu Zissulescu, Bart Kienhuis, Ed F. Depretter...
ASAP
2006
IEEE
169views Hardware» more  ASAP 2006»
14 years 1 months ago
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing
Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a stat...
Hritam Dutta, Frank Hannig, Jürgen Teich, Ben...
CASES
2003
ACM
14 years 24 days ago
Lattice-based memory allocation
—We investigate the problem of memory reuse in order to reduce the memory needed to store an array variable. We develop techniques that can lead to smaller memory requirements in...
Alain Darte, Robert Schreiber, Gilles Villard
ESOP
2003
Springer
14 years 23 days ago
Using Controller-Synthesis Techniques to Build Property-Enforcing Layers
In complex systems, like robot plants, applications are built on top of a set of components, or devices. Each of them has particular individual constraints, and there are also log...
Karine Altisen, Aurélie Clodic, Florence Ma...