184 search results - page 10 / 37 » Modeling Agent-Based Load Balancing with Time Delays |
GLVLSI
2003
IEEE
14 years 25 days ago
2003
IEEE
—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effectiv...
SBACPAD
2004
IEEE
13 years 9 months ago
2004
IEEE
The aim of the paper is to introduce techniques in order to optimize the parallel execution time of sorting on heterogeneous platforms (processors speeds are related by a constant...
ICCD
2001
IEEE
14 years 4 months ago
2001
IEEE
‡ Physical and generic models that analytically couple the array architecture of CMOS SRAMs with the wire lengths and fan-outs along critical paths to decode and sense data are r...
ISQED
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents a two-step, RC-interconnect insensitive linear time-varying (LTV) driver model for gate-level timing calculation. We show how to characterize a driver with the...
ICAS
2009
IEEE
14 years 2 months ago
2009
IEEE
Modern distributed systems that have to avoid performance degradation and system overload require several runtime management decisions for load balancing and load sharing, overloa...