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EUROPAR
2010
Springer
13 years 9 months ago
2010
Springer
Abstract. Performance of the on-chip cache is critical for processor. The multithread program model usually employed by on-chip many-core architectures may have effects on cache ac...
HPCN
2000
Springer
13 years 11 months ago
2000
Springer
We build an analytical model for an application utilizing master-slave paradigm. In the model, only three architecture parameters are used: latency, bandwidth and flop rate. Instea...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latenc...
DEXAW
2009
IEEE
14 years 2 months ago
2009
IEEE
— The use of design patterns usually changes the approach of software design and makes software development relatively easy. This paper extends work on a forensic model for Logic...
SPAA
1990
ACM
14 years 1 days ago
1990
ACM
Multithreading has been proposed as an architectural strategy for tolerating latency in multiprocessors and, through limited empirical studies, shown to offer promise. This paper ...