356 search results - page 27 / 72 » Modeling Cache Sharing on Chip Multiprocessor Architectures |
ASPDAC
2007
ACM
14 years 19 days ago
2007
ACM
- It is attractive to use the OpenMP as a parallel programming model on a Multiprocessor System-On-Chip (MPSoC) because it is easy to write a parallel program in the OpenMP and the...
ASPDAC
2009
ACM
13 years 6 months ago
2009
ACM
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
IPPS
2000
IEEE
14 years 1 months ago
2000
IEEE
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisiti...
PACT
2007
Springer
14 years 2 months ago
2007
Springer
Abstract. It has been already verified that hardware-supported finegrain synchronization provides a significant performance improvement over coarse-grained synchronization mecha...
ICPP
1991
IEEE
14 years 4 days ago
1991
IEEE
-- The Express Ring is a new architecture under investigation at the University of Southern California. Its main goal is to demonstrate that a slotted unidirectional ring with very...