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» Modeling Cache Sharing on Chip Multiprocessor Architectures
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HIPC
1999
Springer
14 years 27 days ago
Process Migration Effects on Memory Performance of Multiprocessor
Abstract. In this work we put into evidence how the memory performance of a WebServer machine may depend on the sharing induced by process migration. We considered a shared-bus sha...
Pierfrancesco Foglia, Roberto Giorgi, Cosimo Anton...
ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
14 years 28 days ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
FPL
2008
Springer
116views Hardware» more  FPL 2008»
13 years 10 months ago
Shared reconfigurable architectures for CMPS
This paper investigates reconfigurable architectures suitable for chip multiprocessors (CMPs). Prior research has established that augmenting a conventional processor with reconfi...
Matthew A. Watkins, Mark J. Cianchetti, David H. A...
HPCA
2006
IEEE
14 years 9 months ago
Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads
With the continuing growth in the amount of genetic data, members of the bioinformatics community are developing a variety of data-mining applications to understand the data and d...
Aamer Jaleel, Matthew Mattina, Bruce L. Jacob
IPCCC
2007
IEEE
14 years 2 months ago
Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study
As Chip Multiprocessor (CMP) has become the mainstream in processor architectures, Intel and AMD have introduced their dual-core processors to the PC market. In this paper, perfor...
Lu Peng, Jih-Kwon Peir, Tribuvan K. Prakash, Yen-K...