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» Modeling Cache Sharing on Chip Multiprocessor Architectures
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IEEEPACT
1998
IEEE
14 years 27 days ago
Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures
The fast evolution of processor performance necessitates a permanent evolution of all the multiprocessor components, even for small to medium-scale symmetric multiprocessors (SMP)...
Wissam Hlayhel, Daniel Litaize, Laurent Fesquet, J...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 2 months ago
ASR: Adaptive Selective Replication for CMP Caches
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
Bradford M. Beckmann, Michael R. Marty, David A. W...
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
14 years 1 months ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
ISCA
2008
IEEE
114views Hardware» more  ISCA 2008»
14 years 3 months ago
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
Future chip multiprocessors (CMPs) may have hundreds to thousands of threads competing to access shared resources, and will require quality-of-service (QoS) support to improve sys...
Jae W. Lee, Man Cheuk Ng, Krste Asanovic
VLDB
2007
ACM
166views Database» more  VLDB 2007»
14 years 2 months ago
To Share or Not To Share?
Intuitively, aggressive work sharing among concurrent queries in a database system should always improve performance by eliminating redundant computation or data accesses. We show...
Ryan Johnson, Nikos Hardavellas, Ippokratis Pandis...