356 search results - page 36 / 72 » Modeling Cache Sharing on Chip Multiprocessor Architectures |
DSD
2009
IEEE
14 years 16 days ago
2009
IEEE
Modern systems are able to put two or more processors on the same die (Chip Multiprocessors, CMP), each with its private caches, while the last level caches can be either private ...
ASPLOS
1991
ACM
14 years 5 days ago
1991
ACM
The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory ...
IPPS
2009
IEEE
14 years 3 months ago
2009
IEEE
Partitioned Global Address Space (PGAS) languages provide a unique programming model that can span shared-memory multiprocessor (SMP) architectures, distributed memory machines, o...
HPCA
1999
IEEE
14 years 29 days ago
1999
IEEE
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not e...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...