356 search results - page 65 / 72 » Modeling Cache Sharing on Chip Multiprocessor Architectures |
116
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HPCA
2009
IEEE
16 years 4 months ago
2009
IEEE
The verification of an execution against memory consistency is known to be NP-hard. This paper proposes a novel fast memory consistency verification method by identifying a new na...
108
Voted
IPPS
2003
IEEE
15 years 8 months ago
2003
IEEE
A number of software packages are available for the construction of comprehensive human genetic maps. In this paper we parallelize the widely used package Genehunter. We restrict ...
131
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ICCCN
2007
IEEE
15 years 9 months ago
2007
IEEE
—The emergence of multi-processor, multi-threaded architectures (referred to as multi- architectures) facilitates the design of high-throughput request processing systems (e.g., ...
122
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DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
Abstract—Addressing both standby and active power is a major challenge in developing System-on-Chip designs for batterypowered products. Powering off sections of logic or memorie...
164
Voted
CODES
2009
IEEE
15 years 10 months ago
2009
IEEE
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...