356 search results - page 9 / 72 » Modeling Cache Sharing on Chip Multiprocessor Architectures |
129
Voted
IPPS
2010
IEEE
15 years 1 months ago
2010
IEEE
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
131
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ICPP
2009
IEEE
15 years 10 months ago
2009
IEEE
Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single c...
112
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ICCAD
2008
IEEE
16 years 11 days ago
2008
IEEE
In this paper, we propose a new architecture-level parameterized transient thermal behavioral modeling algorithm for emerging thermal related design and optimization problems for ...
119
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DAC
2004
ACM
16 years 4 months ago
2004
ACM
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
132
Voted
IEEEPACT
2008
IEEE
15 years 10 months ago
2008
IEEE
Both commercial and scientific workloads benefit from concurrency and exhibit data sharing across threads/processes. The resulting sharing patterns are often fine-grain, with t...