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ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
14 years 2 months ago
Rescue: A Microarchitecture for Testability and Defect Tolerance
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
Ethan Schuchman, T. N. Vijaykumar
RSP
2005
IEEE
164views Control Systems» more  RSP 2005»
14 years 2 months ago
High Level Synthesis for Data-Driven Applications
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley,...
AOSD
2005
ACM
14 years 2 months ago
An expressive aspect language for system applications with Arachne
C applications, in particular those using operating system level services, frequently comprise multiple crosscutting concerns: network protocols and security are typical examples ...
Rémi Douence, Thomas Fritz, Nicolas Loriant...
ASPDAC
2005
ACM
113views Hardware» more  ASPDAC 2005»
14 years 2 months ago
Scalable interprocedural register allocation for high level synthesis
Abstract— The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the depart...
Rami Beidas, Jianwen Zhu
MM
2005
ACM
107views Multimedia» more  MM 2005»
14 years 2 months ago
Spatio-temporal quality assessment for home videos
Compared with the video programs taken by professionals, home videos are always with low-quality content resulted from lack of professional capture skills. In this paper, we prese...
Tao Mei, Cai-Zhi Zhu, He-Qin Zhou, Xian-Sheng Hua
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