78 search results - page 10 / 16 » Modeling QCA for area minimization in logic synthesis |
DAC
2008
ACM
14 years 8 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
GLVLSI
2011
IEEE
12 years 11 months ago
2011
IEEE
Existing optimization algorithms for the multiplierless realization of multiple constant multiplications (MCM) typically target the minimization of the number of addition and subt...
NDJFL
2002
13 years 7 months ago
2002
This paper discusses the relation between the minimal positive relevant logic B+ and intersection and union type theories. There is a marvellous coincidence between these very diff...
ISCA
1999
IEEE
14 years 4 days ago
1999
IEEE
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...