78 search results - page 13 / 16 » Modeling QCA for area minimization in logic synthesis |
ASAP
2009
IEEE
14 years 4 months ago
2009
IEEE
—This paper describes the acceleration of virtual ecology models using field-programmable gate arrays (FPGAs). Our approach targets models generated by the Virtual Ecology Workb...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
MiniBit, our automated approach for optimizing bit-widths of fixed-point designs is based on static analysis via affine arithmetic. We describe methods to minimize both the intege...
ISCA
1997
IEEE
13 years 11 months ago
1997
IEEE
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...
CONSTRAINTS
2007
13 years 7 months ago
2007
In the ECAD area, the Test Generation (TG) problem consists in finding an input vector test for some possible diagnosis (a set of faults) of a digital circuit. Such tests may have ...
FPL
2004
Springer
14 years 12 days ago
2004
Springer
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...