4 search results - page 1 / 1 » Modeling and Estimation of Full-Chip Leakage Current Conside... |
DAC
2007
ACM
14 years 8 months ago
2007
ACM
We present an efficient technique for finding the mean and variance of the full-chip leakage of a candidate design, while considering logic-structures and both die-to-die and with...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
In this paper we address the the growing issue of junction tunneling leakage (Ijunc) at the circuit level. Specifically, we develop a fast approach to analyze the state-dependent ...
DAC
2004
ACM
14 years 24 days ago
2004
ACM
Leakage current has become a stringent constraint in today’s processor designs in addition to traditional constraints on frequency. Since leakage current exhibits a strong inver...
GLVLSI
2007
IEEE
13 years 7 months ago
2007
IEEE
This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networ...