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TC
2010
13 years 2 months ago
Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
Holger Lange, Andreas Koch
FCCM
2008
IEEE
205views VLSI» more  FCCM 2008»
14 years 2 months ago
Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation
The recent turmoil in global credit markets has demonstrated the need for advanced modelling of credit risk, which can take into account the effects of changing economic condition...
David B. Thomas, Wayne Luk
DSD
2007
IEEE
151views Hardware» more  DSD 2007»
13 years 12 months ago
P-Ware: A precise and scalable component-based simulation tool for embedded multiprocessor industrial applications
We present a component-based framework and its supporting simulation tool for joint software-hardware modelling and performance analysis of multiprocessor embedded systems. This j...
Ismail Assayad, Sergio Yovine
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
14 years 2 months ago
Efficient testbench code synthesis for a hardware emulator system
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
Ioannis Mavroidis, Ioannis Papaefstathiou