Sciweavers

2097 search results - page 390 / 420
» Modeling and Simulation of Hardware Software Systems with CD...
Sort
View
DAC
2004
ACM
16 years 4 months ago
Abstraction of assembler programs for symbolic worst case execution time analysis
ion of Assembler Programs for Symbolic Worst Case Execution Time Analysis Tobias Schuele Tobias.Schuele@informatik.uni-kl.de Klaus Schneider Klaus.Schneider@informatik.uni-kl.de Re...
Klaus Schneider, Tobias Schüle
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
15 years 9 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
JUCS
2000
120views more  JUCS 2000»
15 years 2 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
MEMBRANE
2009
Springer
15 years 9 months ago
A Look Back at Some Early Results in Membrane Computing
em is a computing model, which abstracts from the way the living cells process chemical compounds in their compartmental structure. The regions defined by a membrane structure con...
Oscar H. Ibarra
FASE
2006
Springer
15 years 6 months ago
Regular Inference for State Machines with Parameters
Techniques for inferring a regular language, in the form of a finite automaton, from a sufficiently large sample of accepted and nonaccepted input words, have been employed to cons...
Therese Berg, Bengt Jonsson, Harald Raffelt