588 search results - page 36 / 118 » Modeling and Verifying Circuits Using Generalized Relative T... |
ICCAD
1999
IEEE
14 years 9 days ago
1999
IEEE
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
CODES
2007
IEEE
13 years 12 months ago
2007
IEEE
The synchronous computational model with its simple computation and communication mechanism makes it easy to describe, simulate and formally verify synchronous embedded systems at...
ISPD
2010
ACM
14 years 2 months ago
2010
ACM
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
TCAD
2008
13 years 8 months ago
2008
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
FLAIRS
2004
13 years 9 months ago
2004
One fascinating aspect of tool building for datamining is the application of a generalized datamining tool to a specific domain. Often times, this process results in a cross disci...