588 search results - page 42 / 118 » Modeling and Verifying Circuits Using Generalized Relative T... |
103
Voted
VLSID
2002
IEEE
16 years 2 months ago
2002
IEEE
Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming...
112
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ISCAS
2002
IEEE
15 years 7 months ago
2002
IEEE
We have implemented an aspect of learning and memory in the nervous system using analog electronics. Using a simple synaptic circuit we realize networks with Hebbian type adaptati...
122
Voted
DAC
1997
ACM
15 years 6 months ago
1997
ACM
Cr, As the complexity of high-performance microprocessor increases, functional verification becomes more and more difficult and RTL simulation emerges as the bottleneck of the des...
114
Voted
DAC
2005
ACM
16 years 3 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
120
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JSS
2010
15 years 19 days ago
2010
There is a general consensus on the importance of good Requirements Engineering (RE) for achieving high quality software. The modeling and analysis of requirements have been the m...